The present invention relates to a clock data recovery circuit and relates to, for example, a clock data recovery circuit that receives a signal on a transmission line in which a clock is superimposed on data and separates the clock from the data.
In a serial data communication such as PCI express (registered trademark), a signal in which a clock is superimposed on data is used as a transmission signal. Therefore, in the serial data communication, a clock data recovery circuit is used to separate the clock from the data of a reception signal in a reception side. This clock data recovery circuit includes a phase detector that detects a phase difference between an input signal and the clock and extracts data from the input signal, a loop filter that generates a phase control signal from the phase difference detected in the phase detector, and a phase shifter that controls the phase of the clock based on the phase control signal.
In recent years, in accordance with an increase in the communication speed of the serial data communication, a phase delay of an output of the phase detector due to a latency of the loop filter of the clock data recovery circuit has become a problem. One example of techniques for compensating for the latency of the loop filter is disclosed in Japanese Unexamined Patent Application Publication No. 2001-202721.
Japanese Unexamined Patent Application Publication No. 2001-202721 discloses an example of the loop filter mounted on a PLL circuit. The PLL circuit disclosed in Japanese Unexamined Patent Application Publication No. 2001-202721 includes a latency compensation circuit based on the Smith method. More specifically, the loop filter circuit disclosed in Japanese Unexamined Patent Application Publication No. 2001-202721 includes an input circuit that receives a phase signal corresponding to a change in phases and an actual phase signal corresponding to an actual phase sampling of a sampling clock, a filter circuit that connects the phase signal and the actual phase signal to a phase update signal, and a feedback circuit that eliminates loop latency by feeding back to the filter circuit a part of the phase update signal.